The Corigine MimicPro™ Prototyping System is a high-performance, FPGA-based system that raises prototyping to an unprecedented new level. The MimicPro system expedits early software development in areas, such as system validation and regression testing, by significantly reducing development time and workload.

MimicPro Systems

MimicPro Solo (1-FPGA)

MimicPro Quad (4-FPGA)

MimicPro-32 (32-FPGA)


HIGHLIGHTS

Corigine MimicPro system is the leading-edge automated prototyping platform. It provides high performance and equal speed for ASIC and software development for both the Enterprice and Cloud operations without compromising security or scalability.

OPTIMAL VISIBILITY

The MimicPro system offers a system-level view for optimum partitioning. The deep local debug capability enables greater visibility and speedy elimination of bugs. In doing so, MimicPro system substantially reduces the overall development time without the need to purchase pricy emulation.

SCALABILITY

The MimicPro system is equipped with modular upgrabiliy capability for prototyping of an enterprise’s ASICs family, such as AI, processor, vision, communication, and other SOCs. It can scale from 1 to 32 FPGAs depending on business needs. The system can be upgraded easily to the latest available FPGAs.

CLOUD ACCESS & SECURITY

Corigine MimicPro system is designed for operations in both the Enterprise and Cloud environments. Encrypted prototyping in the system is uniquely programmed to ensure security of the user IP. 

DOCUMENTATION

Product Brief




Corigine MimicPro Prototyping System Benefits:

Local Debug and System Scope Logic Analyzer

Provides high visibility for faster logic debug to quickly resolve bugs

System-Level Routing

Delivers highest system performance for software development thus reducing development time

Auto-Partitioning

Reduces manual intervention and R&D workload with automated pin-muxing and instrum entation

User Design Import

Supports both RTL Verilog and System Verilog as well as gate level EDIF

Automatic Clock Handling

Eliminates manual handling of gating clock thus reducing engineering workload and manual errors

Incremental Compilation

Minimizes compilation time

Memory Compiler/Analyzer

Eliminates time consuming recompilation by providing backdoor runtime memory access

Fault Injection

Force/Release capability, supporting automotive safety requirements

Vector Mode

Enables remote cloud deployment based on simulation stimulus

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